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AC39LV010
AC39LV010
1 Megabit (128K x 8) Flash Memory
Single Power Supply - Full voltage range: 2.7 to 3.6 volts for both read and write operations - Regulated voltage range : 3.0 to 3.6 volts for both read and write operations Sector-Erase Capability Uniform 4Kbyte sectors Read Access Time Access time: 45, 70 and 90 ns Power Consumption - Active current: 5 mA (Typical) - Standby current: 1 A (Typical) Erase /Program Features - Sector-Erase Time: 40 ms (Typical) - Chip-Erase Time: 40 ms (Typical) - Byte-Program Time: 11s (Typical) - Chip Rewrite Time: 1.5 seconds (Typical) Automatic Write Timing Internal VPP Generation End-of-Program or End-of-Erase Detection - Data# Polling - Toggle Bit
CMOS I/O Compatibility JEDEC Standard Pin-out and software command sets compatible with single-power supply Flash memory High Reliability - Endurance cycles: 100K (Typical) - Data retention: 10 years Package Option - 32-lead PLCC - 32-pin TSOP - 48-pin FBGA
PRODUCT DESCRIPTION
The AC39LV010 is an 1M bits Flash memory organized as 128K x 8 bits . The AC39LV010 uses single 3.0 volt-only power supply for both Read and Write functions. Featuring high performance Flash memory technology, the AC39LV010 provides a typical Byte-Program time of 11 sec and a typical Sector -Erase time of 40 ms. The device uses Toggle Bit or Data# Polling to detect the completion of the Program or Erase operation. To protect against inadvertent write, the device has on-chip hardware and software data protection schemes. The device offers typical 100,000 cycles endurance and a great er than 10 years data retention. The AC39LV010 conforms to JEDEC standard pin outs for x8 memories. The AC39LV010 is offered in package types of 32-lead PLCC, 32 -pin TSOP, 48-ball FBGA, and known good die (KGD). For KGD, please contact Actrans System Inc. or its representatives for detailed information. The AC39LV010 devices are developed for applications that require memories with convenient and economical updating of program, data or configurations, e.g., Networking cards, Card Readers, Graphic cards, Digital TV, MP3, Wireless Phones, etc.
Contact Information for Actrans System Inc.
2F, No. 9, Industry E. Rd. IV Science Based Industrial Park Hsinchu 300, Taiwan, R.O.C. Tel. (+886-3) 577-8366 Fax. (+886-3) 577-8369 E-mail. service@actrans -inc.com Website. www.actrans -inc.com
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AC39LV010 ORDERING INFORMATION Standard Products
The order number is defined by a combination of the following elements. AC39LV010 -70 F W C Description Temperature Range (1 digit)
C I W E N KGD F = Commercial (0C to +70C) = Industrial (-40C to +85C) = FBGA (0.8mm pitch, 6mm x 8mm) = TSOP (Type 1, die up, 8mm x 14mm) = 32-pin PLCC = Known Good Die (for wafer or dice sell) = PB (Lead) free package
Package Type (1-3 digits)
Speed Option (2-3 digits) 45R = 45ns 70 = 70ns 90 = 90ns ** = VDD = 2.7~3.6V Full voltage range **R = VDD = 3.0~3.6V Regulated voltage range
Device Number/Description
AC39LV010 1 Megabit (128K x 8-Bit) Flash Memory
Valid Combinations for TSOP 32Pin Package AC39LV010-45R EC, EI AC39LV010-70 EC, EI AC39LV010-70R EC, EI AC39LV010-90 EC, EI AC39LV010-90R EC, EI
Valid Combinations for PLCC 32Pin Package AC39LV010-45R NC, NI AC39LV010-70 NC, NI AC39LV010-70R NC, NI AC39LV010-90 NC, NI AC39LV010-90R NC, NI
Valid Combinations for FBGA 48 Ball Package Order Number Package Marking AC39LV010-45R WC, WI V010-45R C, I AC39LV010-70 WC, WI V010-70 C, I AC39LV010-70R WC, WI V010-70R C, I AC39LV010-90 WC, WI V010-90 C, I AC39LV010-90R WC, WI V010-90R C, I Valid Combinations: Valid Combinations list the configurations that are supported in volume for this device.
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AC39LV010 Functional Block Diagram
Flash Memory Array X-Decoder
Memory Address
Address Buffer & Latches Y-Decoder
CE# OE# WE# Control Logic I/O Buffers and Data Latches
DQ7-DQ0
Pin Assignments
A12 A 1 5 A 1 6 N C V DD W E # N C
4
3
2
1
32
31 30
A7 A6 A5 A4 A3 A2 A1 A0 DQ0
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 32-Lead PLCC Top View
29 28 27 26 25 24 23 22 21 20
A14 A13 A8 A9 A11 OE# A10 CE# DQ7
D Q 1 D Q 2 V S S D Q 3D Q 4D Q 5 D Q 6
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AC39LV010 Pin Assignments
A11 A9 A8 A13 A14 NC WE# VDD NC A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Standard TSOP
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
FBGA Top View, Balls Facing Down
A14
A13
A15
A16
A17
NC
NC
V SS
A9
A8
A11
A12
A19
A10
DQ6
DQ7
WE#
NC
NC
NC
DQ5
NC
V DD
DQ4
NC
NC
NC
NC
DQ2
DQ3
V DD
NC
A7
A18
A6
A5
DQ0
NC
NC
DQ1
A3
A4
A2
A1
A0
CE#
OE#
V SS
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AC39LV010 Table 1. PIN DESCRIPTION
Name of the Pin Function A0-A16 17 addresses DQ7-DQ0 Data inputs/outputs CE# Chip enable OE# Output enable WE# Write enable 3.0 volt-only single power supply* VDD Device ground VSS NC Pin not connected internally * Note : see ordering information (page.2) for speed options and voltage supply tolerances
DEVICE OPERATION
The AC39LV010 uses Commands to initiate the memory operation functions. The Commands are written to the device by asserting WE# Low while keeping CE# Low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the AC39LV010 is controlled by CE# and OE#, both have to be Low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram in Figure 1 for further details.
Byte Program
The AC39LV010 is programmed on a byte-by-byte basis. Before programming, the sector where the byte locates must be erased completely. The Program operation is accomplished in three steps. The first step is a three-byte load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last; and the data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 16 s. See Figures 2 and 3 for WE# and CE# controlled Program operation timing diagrams and Figure 12 for flowchart. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored.
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AC39LV010 Table 2: AC39LV010 Device Operation
Operation CE# OE# WE# DQ Read VIL VIL VIH DOUT Program VIL VIH VIL DIN 1 Erase VIL VIH VIL X Standby VIH X X High Z Write Inhibit X VIL X High Z/DOUT Write Inhibit X X VIH High Z/DOUT Software Mode VIL VIL VIH Product Identification Note: X can be VIL or V IH , but no other value. Address AIN AIN Sector address, XXH for Chip-Erase X X X See Table 3
Write Command/Command Sequence
The AC39LV010 provides two software methods to detect the completion of a Program or Erase cycle in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the write operation is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent such spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid.
Chip Erase
The AC39LV010 provides Chip-Erase feature, which allows the entire memory array to be erased to logic "1" state. The Chip-Erase operation is initiated by executing a six-byte command sequence with ChipErase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid reads are Toggle Bit and Data# Polling. See Table 3 for the command sequence, Figure 6 for timing diagram, and Figure 15 for the flowchart. Any commands issued during the Chip-Erase operation are ignored.
Sector Erase
The AC39LV010 offers Sector-Erase mode. The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The Sector-Erase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth WE# pulse, while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit method. See Figures 7 for timing waveforms. A commands issued ny during the Sector Erase operation are ignored.
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AC39LV010 Data# Polling (DQ7)
When the AC39LV010 is in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce the true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Program operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 s. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector Erase or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 4 for Data# Polling timing diagram and Figure 13 for a flowchart.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-Erase or ChipErase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 5 for Toggle Bit timing diagram and Figure 13 for a flowchart.
Data Protection
The AC39LV010 provides both hardware and software features to protect the data from inadvertent write.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# Low, CE# High, or WE# High will inhibit the Write operation. This prevents inadvertent write during power-up or power-down.
Software Data Protection (SDP)
The AC39LV010 provides the JEDEC approved Software Data Protection (SDP) scheme for Program and Erase operations. Any Program operation requires the inclusion of the three-byte sequence. The threebyte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, especially during the system power-up or power-down transition. Any Erase operation requires the inclusion of six-byte sequence. See Table 3 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC .
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AC39LV010 Table 3: Software Command Sequence
Command Sequence 1st Bus Write Cycle Addr 1 Data 5555H AAH 5555H AAH 5555H AAH 5555H AAH 2nd Bus Write Cycle Addr1 Data 2AAAH 55H 2AAAH 55H 2AAAH 55H 2AAAH 55H 3rd Bus 4th Bus 5th Bus 6th Bus Write Cycle Write Cycle Write Cycle Write Cycle Addr1 Data Addr1 Data Addr1 Data Addr 1 Data 2 5555H A0H BA Data 5555H 80H 5555H AAH 2AAAH 55H SAX3 30H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H 5555H 90H
Byte Program Sector Erase Chip Erase Software ID 4,6 Entry Manufacture ID 5555H AAH 2AAAH 55H 5555H 90H 0000H 7FH Manufacture ID 5555H AAH 2AAAH 55H 5555H 90H 0003H 7FH Manufacture ID 5555H AAH 2AAAH 55H 5555H 90H 0040H 1FH Device ID 5555H AAH 2AAAH 55H 5555H 90H 0001H A8H Software ID Exit5 XXH F0H 5 Software ID Exit 5555H AAH 2AAAH 55H 5555H F0H Note: 1. Address format A15-A0 (Hex), Addresses A16 can be VIL or VIH , but no other value, for the Command sequence. 2. BA = Program byte address. 3. SAX for Sector -Erase; uses A16-A12 address lines. 4. The device does not remain in Software Product ID mode if powered down. 5. Both Software ID Exit operations are equivalent. 6. Please refer to figure 9 for more information.
ABSOLUTE MAXIMUM RATINGS (Applied conditions greater than those listed under "Absolute
Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias ..................................................................................... -55C to 125C Storage Temperature ............................................................................................ -65C to 150C D.C. Voltage on Any Pin to Ground Potential ...................................................... -0.5 V to V DD+0.5V Transient Voltage (<20ns) on Any Pin to Ground Potential..................................... -2.0V to VDD +2.0V Voltage on A9 Pin to Ground Potential..................................................................... -0.5 V to 13.2V Package Power Dissipation Capability (Ta=25C).................................................................... 1.0W Surface Mount Lead Soldering Temperature (3 Seconds)......................................................... 240C Output Short Circuit Current (Note 1).....................................................................................50mA Note 1: Output shorted for no more than one second. No more than one output shorted at a time.
Table 4: Operating Range
Model Name AC39LV010 Industrial -40C to +85C Range Commercial Ambient Temperature 0C to +70C VDD Full voltage range : 2.7~3.6V Regulated voltage range : 3.0~3.6V Full voltage range : 2.7~3.6V Regulated voltage range : 3.0~3.6V
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AC39LV010 AC CONDITIONS OF TEST
Input Rise/Fall Time..................................................................................5ns Output Load............................................................................................CL=30pF for 45Rns Output Load............................................................................................CL=100pF for 70ns/90ns See Figures 10 and 11
Table 5: DC CHARACTERISTICS (CMOS Compatible)
Parameter Description IDD Power Supply Current Read Program and Erase Standby VDD Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Input High Voltage (CMOS) Output Low Voltage Output High Voltage Test Conditions Address Input =VIL/VIH , at f=1/TRC Min, VDD=VDD Max CE#=OE#=VIL, WE#=VIH, all I/Os open CE#=WE#=VIL, OE#=VIH, CE#=VIHC , VDD=VDD Max VIN=GND to VDD, VDD =VDD Max VOUT=GND to VDD, VDD =VDD Max VDD=VDD Min VDD=VDD Max VDD=VDD Max IOL=100 A, VDD=VDD Min IOH=-100A, VDD =VDD Min 0.7 VDD VDD -0.3 0.2 VDD -0.2 Min Max Unit
ISB ILI ILO VIL VIH VIHC VOL VOH
20 30 15 1 10 0.8
mA mA A A A V V V V V
Table 6: Recommended System Power-up Timing
Parameter Description Min Unit 1 TPU-READ Power-up to Read Operation 100 s 1 TPU-WRITE Power-up to Program/Erase Operation 100 s Note: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Table 7: Capacitance (Ta=25 C, f=1Mhz, other pins open)
Parameter Description Test Conditions Max 1 CI/O I/O Pin Capacitance VI/O=0V 12pF CIN 1 Input Capacitance VIN=0V 6pF Note: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Table 8: Reliability Characteristics
Symbol Parameter Min Specification Unit Test Method 1 NEND Endurance 10,000 Cycles JEDEC Standard A117 1 TDR Data Retention 10 Years JEDEC Standard A103 1 ILTH Latch Up 100+IDD mA JEDEC Standard 78 Note: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
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AC39LV010 AC CCHARACTERISTICS Table 9: Read Cycle Timing Parameters
Symbol TRC TCE TAA TOE 1 TCLZ 1 TOLZ 1 TCHZ 1 TOHZ 1 TOH Symbol Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change Parameter 45REC Min Max 45 45 45 30 0 0 15 15 0 45EC Max 70REC Min Max 70 70 70 35 0 0 25 25 0 70EC Min 70 Max Min 90 90REC Min Max 90 90 90 45 0 0 30 30 0 90EC Max Unit ns ns ns ns ns ns ns ns ns Unit ns ns ns ns ns ns ns ns ns
TRC Read Cycle Time TCE Chip Enable Access Time 45 70 90 TAA Address Access Time 45 70 90 TOE Output Enable Access Time 30 35 45 1 TCLZ CE# Low to Active Output 0 0 0 1 TOLZ OE# Low to Active Output 0 0 0 1 TCHZ CE# High to High-Z Output 15 25 30 1 TOHZ OE# High to High-Z Output 15 25 30 1 TOH Output Hold from Address Change 0 0 0 Note: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Min 45
Table 10: Program/Erase Cycle Timing Parameter
Symbol TBP TAS TAH TCS TCH TOES TOEH TCP TWP TWPH 1 1 TCPH TDS 1 TDH TIDA1 TSE TSCE Parameter Byte-Program Time Address Setup Time Address Hold Time WE# and CE# Setup Time WE# and CE# Hold Time OE# High Setup Time OE# High Hold Time CE# Pulse Width WE# Pulse Width WE# Pulse Width High CE# Pulse Width High Data Setup Time Data Hold Time Software ID Access and Exit Time Sector Erase Chip Erase Min 0 30 0 0 0 10 40 40 30 30 40 0 150 60 60 Max 16 Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms
Note: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
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AC39LV010
TRC A16~A0 TCE
TAA
CE#
OE#
TOE
TO L Z
TOHZ
V IH WE#
T CLZ
TOH Data Valid
TCHZ Data Valid HIGH-Z
HIGH-Z DQ7-0
Figure 1. Read Cycle Timing Diagram
Internal Program Operation Starts TBP A16~A0 5555 TA H WE# TW P TWPH TA S OE# T DS 2AAA 5555 ADDR TDH
TCH CE# TCS DQ7-0 AA SW0 55 SW1 A0 SW2 DATA Byte (ADDR/DATA)
Figure 2. WE# Controlled Program Cycle Timing Diagram
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AC39LV010
Internal Program Operation Starts T BP A16~A0 5555 TAH TCP CE# TCPH TAS OE# T DS 2AAA 5555 ADDR TDH
TCH WE#
TCS DQ7-0 AA SW0 55 SW1 A0 SW2 DATA Byte (ADDR/DATA)
Figure 3. CE# Controlled Program Cycle Timing Diagram
A16~A0 TCE CE# TOEH OE# TOE WE# TOES
DQ7
DATA
DATA#
DATA#
DATA#
Figure 4. Data# Polling Timing Diagram
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AC39LV010
A16~A0 TCE CE# T OEH OE# TOE T OES
WE#
DQ6 Two Read Cycles With Same Outputs
Figure 5. Toggle Bit Timing Diagram
Six-Byte Code For Chip-Erase
TSCE 5555
A16~A0
5555
2AAA
5555
5555
2AAA
CE#
OE# TW P WE#
DQ7-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
10 SW5
Note: This device also supports CE# controlled Chip-Erase operation. The WE#and CE# signals are interchageable as long as minimum timings are met. (See Table 10)
Figure 6. WE# Controlled Chip-Erase Timing Diagram
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AC39LV010
Six-Byte Code For Sector-Erase
TSE SAX
A16~A0
5555
2AAA
5555
5555
2AAA
CE#
OE# TWP WE#
DQ7-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
30 SW5
Note: This device also supports CE# controlled Sector-Erase operation. The WE#and CE# signals are interchageable as long as minimum timings are met. (See Table 10) S A X= S e c t o r A d d r e s s X c a n b e V IL o r V I H , b u t n o o t h e r v a l u e .
Figure 7. WE# Controlled Sector-Erase Timing Diagram
Three-Byte Sequence For Software ID Entry
Address A14-0
5555
2AAA
5555
0 0 0 0 H 0 0 0 3 H 0 0 4 0 H0 0 0 1 H
CE#
OE# TW P WE# TWPH DQ7-0 AA SW0 55 SW1 90 SW2 T AA
7F 7F 1F A8
T IDA
Figure 8. Software ID Entry and Read
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AC39LV010
Three-Byte Sequence For Software ID Exit and Reset
Address A14-0
5555
2AAA
5555
DQ7-0
AA
55
F0 TIDA
CE#
OE# TWP WE# S W 0 T WPH S W 1 SW2
Figure 9. Software ID Exit and Reset
VIHT Input VILT AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT(0.1 VDD) for a logic "0". Measurement reference points for inputs and outpputs are VIT(0.5 VDD) and VOT(0.5 VDD). Input rise and fall times(10% - 90% ) are <5ns VIT Reference Points VOT Output
Note: VIT = Vinput Test VOT = Voutput Test VIHT = Vinput HIGH Test VILT = Vinput LOW Test
Figure 10. AC Input/Output Reference Waveforms
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AC39LV010
TO TESTER
TO DUT CL
Figure 11. A Test Load Example
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AC39LV010
Start
Load Data: AAH Address: 5555H
Load Data: 55H Address: 2AAAH
Load Data: A0H Address: 5555H
Load Byte Address/Byte Data
Wait for end of Program (T B P , D a t a # P o l l i n g b i t , o r Toggle bit operation)
Program Completed
Figure 12. Byte-Program Algorithm
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Figure 20. Temporary Sector Unprotect Timing Diagram
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AC39LV010
Internal Timer Progrm/Erase Initiated Toggle Bit Progrm/Erase Initiated
Data# Polling Progrm/Erase Initiated
Wait T B P , TS C E , T S E or T B E
Read Byte
Read DQ7
Progrm/Erase Completed
Read Same Byte
Is DQ7=true data? Yes
No
Does DQ6 match? Yes Progrm/Erase Completed
No
Progrm/Erase Completed
Figure 13. Wait Options
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AC39LV010
Software ID Entry Command Sequence Load Data: AAH Address: 5555H Software ID Exit Command Sequence Load Data: AAH Address: 5555H Load Data: F0H Address: XXH
Load Data: 55H Address: 2AAAH
Load Data: 55H Address: 2AAAH
Wait T
IDA
Load Data: 90H Address: 5555H
Load Data: F0H Address: 5555H
Return to Normal Operation
Wait TI D A
Wait T
IDA
Read Software ID
Return to Normal Operation
X can be VIL or VIH, but no other value.
Figure 14. Software ID Command Flowcharts
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AC39LV010
Chip-Erase Command Sequence
Sector-Erase Command Sequence
Load Data: AAH Address: 5555H
Load Data: AAH Address: 5555H
Load Data: 55H Address: 2AAAH
Load Data: 55H Address: 2AAAH
Load Data: 80H Address: 5555H
Load Data: 80H Address: 5555H
Load Data: AAH Address: 5555H
Load Data: AAH Address: 5555H
Load Data: 55H Address: 2AAAH
Load Data: 55H Address: 2AAAH
Load Data: 10H Address: 5555H
Load Data: 30H Address: SA
X
Wait T
SCE
Wait T
SE
Chip Erased to FFH
Sector Erased to FFH
X can be VIL or VIH, but no other value.
Figure 15. Erase Command Sequence
w w w This preliminary data sheetU . c o product specifications which are subject to change without notice. . D a t a S h e e t 4 contains m
Page 20
Rev. 1.0 (6/4/04)

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